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1. general description the PCA9511A is a hot swappable i 2 c-bus and smbus buffer that allows i/o card insertion into a live backplane without corrupting the data and clock buses. control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. when the connection is made, the PCA9511A provides bidirectional buffering, keeping the backplane and card capacitances isolated. the PCA9511A rise time accelerator circuitry allows the use of weaker dc pull-up currents while still meeting rise time requirements. the PCA9511A incorporates a digital enable input pin, which enables the device when asserted high and forces the device into a low current mode when asserted low, and an open-drain ready output pin, which indicates that the backplane and card sides are connected together (high) or not (low). during insertion, the PCA9511A sda and scl lines are precharged to 1 v to minimize the current required to charge the parasitic capacitance of the chip. 2. features n bidirectional buffer for sda and scl lines increases fan out and prevents sda and scl corruption during live board insertion and removal from multipoint backplane systems n compatible with i 2 c-bus standard-mode, i 2 c-bus fast-mode, and smbus standards n built-in d v /d t rise time accelerators on all sda and scl lines (0.6 v threshold) requires the bus pull-up voltage and supply voltage (v cc ) to be the same n active high enable input n active high ready open-drain output n high-impedance sda and scl pins for v cc =0v n 1 v precharge on all sda and scl lines n supporting clock stretching and multiple master arbitration/synchronization n operating power supply voltage range: 2.7 v to 5.5 v n 0 hz to 400 khz clock frequency n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n packages offered: so8, tssop8 (msop8) PCA9511A hot swappable i 2 c-bus and smbus bus buffer rev. 04 19 august 2009 product data sheet
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 2 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 3. applications n cpci, vme, advancedtca cards and other multipoint backplane cards that are required to be inserted or removed from an operating system 4. feature selection 5. ordering information [1] also known as msop8. table 1. feature selection chart feature pca9510a PCA9511A pca9512a pca9513a pca9514a idle detect yes yes yes yes yes high-impedance sda, scl pins for v cc = 0 v yes yes yes yes yes rise time accelerator circuitry on sdan and scln lines - yes yes yes yes rise time accelerator circuitry hardware disable pin for lightly loaded systems --yes-- rise time accelerator threshold 0.8 v versus 0.6 v improves noise margin ---yesyes ready open-drain output yes yes - yes yes two v cc pins to support 5 v to 3.3 v level translation with improved noise margins --yes-- 1 v precharge on all sda and scl lines in only yes yes - - 92 m a current source on sclin and sdain for picmg applications ---yes- table 2. ordering information t amb = - 40 c to +85 c type number topside mark package name description version PCA9511Ad pa9511a so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 PCA9511Adp 9511a tssop8 [1] plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 3 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 6. block diagram fig 1. block diagram of PCA9511A 002aab580 100 k w rch3 1 volt precharge 100 k w rch4 100 k w rch1 100 k w rch2 connect enable backplane-to-card connection slew rate detector slew rate detector connect connect 2 ma 2 ma backplane-to-card connection slew rate detector slew rate detector connect connect 2 ma 2 ma sdain sclin 0.5 pf sclout rd s qb uvlo 20 pf 0.55v cc / 0.45v cc 0.5 m a stop bit and bus idle 0.55v cc / 0.45v cc 100 m s delay uvlo enable sdaout v cc connect connect ready gnd PCA9511A
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 4 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 7. pinning information 7.1 pinning 7.2 pin description 8. functional description refer to figure 1 bloc k diag r am of PCA9511A . 8.1 start-up an undervoltage/initialization circuit holds the parts in a disconnected state which presents high-impedance to all sda and scl pins during power-up. a low on the enable pin also forces the parts into the low current disconnected state when the i cc is essentially zero. as the power supply is brought up and the enable is high or the part is powered and the enable is taken from low to high it enters an initialization state where the internal references are stabilized and the precharge circuit is enabled. at the end of the initialization state the stop bit and bus idle detect circuit is enabled. with the enable pin high long enough to complete the initialization state (t en ) and remaining high when all the sda and scl pins have been high for the bus idle time or when all pins are high and a stop condition is seen on the sdain and sclin pins, sdain is connected to sdaout and sclin is connected to sclout. the 1 v precharge circuitry fig 2. pin con?guration for so8 fig 3. pin con?guration for tssop8 enable v cc sclout sdaout sclin sdain gnd ready 002aab577 1 2 3 4 6 5 8 7 PCA9511Ad PCA9511Adp enable v cc sclout sdaout sclin sdain gnd ready 002aab578 1 2 3 4 6 5 8 7 table 3. pin description symbol pin description enable 1 chip enable. grounding this input puts the part in a low current (< 1 m a) mode. it also disables the rise time accelerators, isolates sdain from sdaout and isolates sclin from sclout. sclout 2 serial clock output to and from the scl bus on the card sclin 3 serial clock input to and from the scl bus on the backplane gnd 4 ground. connect this pin to a ground plane for best results. ready 5 open-drain output which pulls low when sdain and sclin are disconnected from sdaout and sclout, and goes high when the two sides are connected sdain 6 serial data input to and from the sda bus on the backplane sdaout 7 serial data output to and from the sda bus on the card v cc 8 power supply
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 5 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer is activated during the initialization and is deactivated when the connection is made. the precharge circuitry pulls up the sda and scl pins to 1 v through individual 100 k w nominal resistors. this precharges the pins to 1 v to minimize the worst case disturbances that result from inserting a card into the backplane where the backplane and the card are at opposite logic levels. 8.2 connect circuitry once the connection circuitry is activated, the behavior of sdain and sdaout as well as sclin and sclout become identical with each acting as a bidirectional buffer that isolates the input capacitance from the output bus capacitance while communicating the logic levels. a low forced on either sdain or sdaout will cause the other pin to be driven to a low by the part. the same is also true for the scl pins. noise between 0.7v cc and v cc is generally ignored because a falling edge is only recognized when it falls below 0.7v cc with a slew rate of at least 1.25 v/ m s. when a falling edge is seen on one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small voltage above the falling pin. the driver will pull the pin down at a slew rate determined by the driver and the load initially, because it does not start until the ?rst falling pin is below 0.7v cc . the ?rst falling pin may have a fast or slow slew rate, if it is faster than the pull down slew rate then the initial pull-down rate will continue. if the ?rst falling pin has a slow slew rate then the second pin will be pulled down at its initial slew rate only until it is just above the ?rst pin voltage then they will both continue down at the slew rate of the ?rst. once both sides are low they will remain low until all the external drivers have stopped driving lows. if both sides are being driven low to the same value for instance, 10 mv by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving that pin will rise until the internal driver pulls it down to the offset voltage. when the last external driver stops driving a low, that pin will rise up and settle out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the rc time constant. as long as the slew rate is at least 1.25 v/ m s, when the pin voltage exceeds 0.6 v for the PCA9511A, the rise time accelerators circuits are turned on and the pull-down driver is turned off. 8.3 maximum number of devices in series each buffer adds about 0.1 v dynamic level offset at 25 c with the offset larger at higher temperatures. maximum offset (v offset ) is 0.150 v with a 10 k w pull-up resistor. the low level at the signal origination end (master) is dependent upon the load and the only speci?cation point is that the i 2 c-bus speci?cation of 3 ma will produce v ol < 0.4 v, although if lightly loaded the v ol may be ~0.1 v. assuming v ol = 0.1 v and v offset = 0.1 v, the level after four buffers would be 0.5 v, which is only about 0.1 v below the threshold of the rising edge accelerator (about 0.6 v). with great care a system with four buffers may work, but as the v ol moves up from 0.1 v, noise or bounces on the line will result in ?ring the rising edge accelerator thus introducing false clock edges. generally it is recommended to limit the number of buffers in series to two, and to keep the load light to minimize the offset. the pca9510a (rise time accelerator is permanently disabled) and the pca9512a (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 6 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer on the accelerator turns the pull-down off. if the v il is above ~0.6 v and a rising edge is detected, the pull-down will turn off and will not turn back on until a falling edge is detected. consider a system with three buffers connected to a common node and communication between the master and slave b that are connected at either end of buffer a and buffer b in series as shown in figure 4 . consider if the v ol at the input of buffer a is 0.3 v and the v ol of slave b (when acknowledging) is 0.4 v with the direction changing from master to slave b and then from slave b to master. before the direction change you would observe v il at the input of buffer a of 0.3 v and its output, the common node, is ~0.4 v. the output of buffer b and buffer c would be ~0.5 v, but slave b is driving 0.4 v, so the voltage at slave b is 0.4 v. the output of buffer c is ~0.5 v. when the master pull-down turns off, the input of buffer a rises and so does its output, the common node, because it is the only part driving the node. the common node will rise to 0.5 v before buffer bs output turns on, if the pull-up is strong the node may bounce. if the bounce goes above the threshold for the rising edge accelerator ~0.6 v the accelerators on both buffer a and buffer c will ?re contending with the output of buffer b. the node on the input of buffer a will go high as will the input node of buffer c. after the common node voltage is stable for a while the rising edge accelerators will turn off and the common node will return to ~0.5 v because the buffer b is still on. the voltage at both the master and slave c nodes would then fall to ~0.6 v until slave b turned off. this would not cause a failure on the data line as long as the return to 0.5 v on the common node (~0.6 v at the master and slave c) occurred before the data setup time. if this were the scl line, the parts on buffer a and buffer c would see a false clock rather than a stretched clock, which would cause a system error. 8.4 propagation delays the delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. if the pull-up currents are the same, any difference in rise time is directly proportional to the difference in capacitance between the two sides. the t plh may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. the t phl can never be negative because the output does not start to fall until the input is below 0.7v cc , and the output turn on has a non-zero delay, and the output has a limited maximum slew rate, and even if the input slew rate is slow enough that the output catches up it will still lag the falling voltage of the input by the offset voltage. the maximum t phl occurs when the input is driven low with zero delay and the output is still limited by its fig 4. system with 3 buffers connected to common node 002aab581 buffer c buffer b buffer a common node slave b slave c master
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 7 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer turn-on delay and the falling edge slew rate. the output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature, v cc and process, as well as the load current and the load capacitance. 8.5 rise time accelerators during positive bus transitions a 2 ma current source is switched on to quickly slew the sda and scl lines high once the input level of 0.6 v for the PCA9511A is exceeded. the rising edge rate should be at least 1.25 v/ m s to guarantee turn on of the accelerators. the built-in d v /d t rise time accelerators on all sda and scl lines requires the bus pull-up voltage and supply voltage (v cc ) to be the same. 8.6 ready digital output this pin provides a digital ?ag which is low when either enable is low or the start-up sequence described earlier in this section has not been completed. ready goes high when enable is high and start-up is complete. the pin is driven by an open-drain pull-down capable of sinking 3 ma while holding 0.4 v on the pin. connect a resistor of 10 k w to v cc to provide the pull-up. 8.7 enable low current disable grounding the enable pin disconnects the backplane side from the card side, disables the rise time accelerators, drives ready low, disables the bus precharge circuitry, and puts the part in a low current state. when the pin voltage is driven all the way to v cc , the part waits for data transactions on both the backplane and card sides to be complete before reconnecting the two sides. 8.8 resistor pull-up value selection the system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 v/ m s on the sda and scl pins, in order to activate the boost pull-up currents during rising edges. choose maximum resistor value using the formula given in equation 1 : (1) where r is the pull-up resistor value in w , v cc(min) is the minimum v cc voltage in volts, and c is the equivalent bus capacitance in picofarads (pf). in addition, regardless of the bus capacitance, always choose r 65.7 k w for v cc = 5.5 v maximum, r 45 k w for v cc = 3.6 v maximum. the start-up circuitry requires logic high voltages on sdaout and sclout to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. see the curves in figure 5 and figure 6 for guidance in resistor pull-up selection. r 800 10 3 v cc min () 0.6 C c ----------------------------------- ? ??
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 8 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer (1) unshaded area indicates recommended pull-up, for rise time < 300 ns, with PCA9511A. (2) rise time without PCA9511A. fig 5. bus requirements for 3.3 v systems (1) unshaded area indicates recommended pull-up, for rise time < 300 ns, with PCA9511A. (2) rise time without PCA9511A. fig 6. bus requirements for 5 v systems c b (pf) 0 400 300 200 100 002aae780 20 10 30 50 r pu (k w ) 0 r max = 45 k w rise time = 20 ns r min = 1 k w rise time = 300 ns (2) 40 (1) c b (pf) 0 400 300 200 100 002aae781 70 r pu (k w ) 0 10 20 30 40 50 60 (1) r max = 65.7 k w rise time = 20 ns r min = 1.7 k w rise time = 300 ns (2)
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 9 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 8.9 hot swapping and capacitance buffering application figure 7 through figure 10 illustrate the usage of the PCA9511A in applications that take advantage of both its hot swapping and capacitance buffering features. in all of these applications, note that if the i/o cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise time and fall time requirements dif?cult to meet. placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. for a given i/o card, the PCA9511A drives the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pf, the connector, trace, and all additional cards on the backplane. see application note an10160, hot swap bus buffer for more information on applications and technical assistance. remark: the PCA9511A can be used in any combination depending on the number of rise time accelerators that are needed by the system. normally only one PCA9511A would be required per bus. fig 7. hot swapping multiple i/o cards into a backplane using the PCA9511A in a cpci, vme, and advancedtca system 002aab584 r4 10 k w c1 0.01 m f sdaout sclout ready v cc gnd r5 10 k w r6 10 k w r3 10 k w enable sdain sclin power supply hot swap card1_sda card1_scl staggered connector i/o peripheral card 1 backplane connector r8 10 k w c3 0.01 m f sdaout sclout ready v cc gnd r9 10 k w r10 10 k w r7 10 k w enable sdain sclin power supply hot swap card2_sda card2_scl staggered connector i/o peripheral card 2 r12 10 k w c5 0.01 m f sdaout sclout ready v cc gnd r13 10 k w r14 10 k w r11 10 k w enable sdain sclin power supply hot swap cardn_sda cardn_scl staggered connector i/o peripheral card n r2 10 k w r1 10 k w v cc backplane bd_sel sda scl
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 10 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer fig 8. hot swapping multiple i/o cards into a backplane using the PCA9511A in a pci system 002aab585 r4 10 k w c1 0.01 m f sdaout sclout ready v cc gnd r5 10 k w r6 10 k w enable sdain sclin card1_sda card1_scl staggered connector i/o peripheral card 1 backplane connector r8 10 k w c3 0.01 m f sdaout sclout ready v cc gnd r9 10 k w r10 10 k w enable sdain sclin card2_sda card2_scl staggered connector i/o peripheral card 2 r2 10 k w r1 10 k w v cc backplane sda scl c4 0.01 m f c2 0.01 m f remark: see application note an255, i 2 c repeaters, hubs, and expanders for more information on other devices better optimized for long distance transmission of the i 2 c-bus or smbus. fig 9. repeater/bus extender application using the PCA9511A 002aab586 r7 10 k w c2 0.01 m f sdaout sclout ready v cc gnd enable sdain sclin r8 10 k w v cc sda1 scl1 to other system 2 devices i 2 c-bus system 2 r6 10 k w r4 10 k w c1 0.01 m f sdaout sclout ready v cc gnd enable sdain sclin r1 10 k w v cc = 5 v sda1 scl1 to other system 1 devices i 2 c-bus system 1 r5 10 k w long distance bus r3 10 k w r2 10 k w
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 11 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 9. application design-in information 10. limiting values [1] voltages with respect to pin gnd. v cc >v cc_low r drop is the line loss of v cc in the backplane. fig 10. system with disparate v cc voltages 002aab587 r4 10 k w c2 0.01 m f sdaout sclout ready v cc gnd enable sdain sclin r1 10 k w v cc sda scl r5 10 k w r drop v cc_low r2 10 k w r3 10 k w sda2 scl2 fig 11. typical application 002aab579 enable ready gnd 4 5 7 2 r5 10 k w r3 10 k w r4 10 k w sclout sdaout 1 6 3 c1 0.01 m f 8 r1 10 k w r2 10 k w v cc (2.7 v to 5.5 v) sclin sdain enable table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage [1] - 0.5 +7 v v n voltage on sdain, sclin, sdaout, sclout, ready, enable [1] - 0.5 +7 v t oper operating temperature - 40 +85 c t stg storage temperature - 65 +150 c t sp solder point temperature 10 s max. - +300 c t j(max) maximum junction temperature - +125 c
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 12 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 11. characteristics table 5. characteristics v cc = 2.7 v to 5.5 v; t amb = - 40 c to +85 v; unless otherwise speci?ed. symbol parameter conditions min typ max unit power supply v cc supply voltage [1] 2.7 - 5.5 v i cc supply current v cc = 5.5 v; v sdain =v sclin =0v [1] - 3.5 6 ma i cc(sd) shut-down mode supply current v enable = 0 v; all other pins at v cc or gnd - 0.1 - m a start-up circuitry v pch precharge voltage sda, scl ?oating [1] 0.8 1.1 1.2 v v ih(enable) high-level input voltage on pin enable - 0.5 v cc 0.7 v cc v v il(enable) low-level input voltage on pin enable 0.3 v cc 0.5 v cc -v i i(enable) input current on pin enable v enable = 0 v to v cc - 0.1 1 m a t en enable time [2] - 110 - m s t idle(ready) bus idle time to ready active [1] 50 105 200 m s t dis(en-rdy) disable time (enable to ready) -30-ns t stp(ready) sdain to ready delay after stop [3] - 1.2 - m s t ready sclout/sdaout to ready delay [3] - 0.8 - m s i lz(ready) off-state leakage current on pin ready v enable =v cc - 0.3 - m a c i(enable) input capacitance on pin enable v i =v cc or gnd [4] - 1.9 4.0 pf c o(ready) output capacitance on pin ready v i =v cc or gnd [4] - 2.5 4.0 pf v ol(ready) low-level output voltage on pin ready i pu = 3 ma; v enable =v cc [1] - - 0.4 v rise time accelerators i trt(pu) transient boosted pull-up current positive transition on sda, scl; v cc = 2.7 v; slew rate = 1.25 v/ m s [5] [6] 12-ma
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 13 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer [1] this speci?cation applies over the full operating temperature range. [2] the enable time can slow considerably for some parts when temperature is < - 20 c. [3] delays that can occur after enable and/or idle times have passed. [4] guaranteed by design, not production tested. [5] i trt(pu) varies with temperature and v cc voltage, as shown in section 11.1 t ypical perf or mance char acter istics . [6] input pull-up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage to the positive supply rail. [7] the connection circuitry always regulates its output to a higher voltage than its input. the magnitude of this offset voltage as a function of the pull-up resistor and v cc voltage is shown in section 11.1 t ypical perf or mance char acter istics . [8] c b = total capacitance of one bus line in pf. input-output connection v offset offset voltage 10 k w to v cc on sda, scl; v cc = 3.3 v [1] [7] [9] 0 110 175 mv t plh low to high propagation delay scl to scl and sda to sda; 10 k w to v cc ; c l = 100 pf each side -0-ns t phl high to low propagation delay scl to scl and sda to sda; 10 k w to v cc ; c l = 100 pf each side -70-ns c i(scl/sda) scl and sda input capacitance [4] - 57pf v ol low-level output voltage v i = 0 v; sdan, scln pins; i sink = 3 ma; v cc = 2.7 v [1] 0 - 0.4 v i li input leakage current sdan, scln pins; v cc = 5.5 v - 1-+1 m a system characteristics f scl scl clock frequency [4] 0 - 400 khz t buf bus free time between a stop and start condition [4] 1.3 - - m s t hd;sta hold time (repeated) start condition [4] 0.6 - - m s t su;sta set-up time for a repeated start condition [4] 0.6 - - m s t su;sto set-up time for stop condition [4] 0.6 - - m s t hd;dat data hold time [4] 300 - - ns t su;dat data set-up time [4] 100 - - ns t low low period of the scl clock [4] 1.3 - - m s t high high period of the scl clock [4] 0.6 - - m s t f fall time of both sda and scl signals [4] [8] 20 + 0.1 c b - 300 ns t r rise time of both sda and scl signals [4] [8] 20 + 0.1 c b - 300 ns table 5. characteristics continued v cc = 2.7 v to 5.5 v; t amb = - 40 c to +85 v; unless otherwise speci?ed. symbol parameter conditions min typ max unit
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 14 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer [9] force v sdain = v sclin = 0.1 v, tie sdaout and sclout through 10 k w resistor to v cc and measure the sdaout and sclout output. 11.1 typical performance characteristics fig 12. i cc versus temperature fig 13. i trt(pu) versus temperature c i =c o > 100 pf; r pu(in) =r pu(out) =10k w fig 14. input/output t phl versus temperature fig 15. connection circuitry v o - v i t amb ( c) - 40 +90 +25 002aab588 2.9 3.3 3.7 i cc (ma) 2.5 3.3 v v cc = 5.5 v 2.7 v t amb ( c) - 40 +90 +25 002aab590 4 8 12 i trt(pu) (ma) 0 3.0 v v cc = 5 v 2.7 v t amb ( c) - 40 +90 +25 002aab589 70 80 90 t phl (ns) 60 3.3 v v cc = 5.5 v 2.7 v r pu (k w ) 040 30 10 20 002aab591 150 250 350 v o - v i (mv) 50 v cc = 5 v 3.3 v
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 15 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 11.2 timing diagrams fig 16. timing for t en , t idle(ready) , and t dis 002aab592 t en sdan/scln enable ready t idle(ready) t dis t stp(ready) is only applicable after the t en delay. fig 17. t stp(ready) that can occur after t en 002aab593 t en sclin sclout sdaout enable ready t stp(ready) sdain t stp(ready) is only applicable after the t en delay. fig 18. t stp(ready) delay that can occur after t en and t idle(ready) 002aab594 t en t idle(ready) sclin, sdain, sclout, sdaout enable ready t stp(ready)
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 16 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 12. test information r l = load resistor c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to the output impedance z 0 of the pulse generators. fig 19. test circuitry for switching times pulse generator v o c l 100 pf r l 10 k w 002aab595 r t v i v cc v cc dut
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 17 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 13. package outline fig 20. package outline sot96-1 (so8) unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 18 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer fig 21. package outline sot505-1 (tssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.70 0.35 6 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot505-1 99-04-09 03-02-18 w m b p d z e 0.25 14 8 5 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 1.1 pin 1 index
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 19 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 20 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 14.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 22 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 6 and 7 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 22 . table 6. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 7. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 21 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 15. abbreviations msl: moisture sensitivity level fig 22. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 8. abbreviations acronym description advancedtca advanced telecommunications computing architecture cdm charged device model cpci compact peripheral component interface esd electrostatic discharge hbm human body model i 2 c-bus inter ic bus mm machine model pci peripheral component interface picmg pci industrial computer manufacturers group smbus system management bus vme versamodule eurocard
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 22 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 16. revision history table 9. revision history document id release date data sheet status change notice supersedes PCA9511A_4 20090819 product data sheet - PCA9511A_3 modi?cations: ? section 8.8 resistor pull-up v alue selection , 2 nd paragraph, 1 st sentence: changed from ... always choose r 16 k w for v cc = 5.5 v maximum, r 24 k w for v cc = 3.6 v maximum. to ... always choose r 65.7 k w for v cc = 5.5 v maximum, r 45 k w for v cc = 3.6 v maximum. ? figure 5 bus requirements f or 3.3 v systems updated: C changed from rise time > 300 ns to rise time = 300 ns C changed from rise time < 20 ns to rise time = 20 ns ? figure 6 bus requirements f or 5 v systems updated: C changed from rise time > 300 ns to rise time = 300 ns C changed from rise time < 20 ns to rise time = 20 ns PCA9511A_3 20090720 product data sheet - PCA9511A_2 PCA9511A_2 20090528 product data sheet - PCA9511A_1 PCA9511A_1 (9397 750 13269) 20050815 product data sheet - -
PCA9511A_4 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 04 19 august 2009 23 of 24 nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 17.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 17.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 17.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors PCA9511A hot swappable i 2 c-bus and smbus bus buffer ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 19 august 2009 document identifier: PCA9511A_4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 feature selection . . . . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 4 8.1 start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8.2 connect circuitry. . . . . . . . . . . . . . . . . . . . . . . . 5 8.3 maximum number of devices in series . . . . . . . 5 8.4 propagation delays . . . . . . . . . . . . . . . . . . . . . . 6 8.5 rise time accelerators . . . . . . . . . . . . . . . . . . . 7 8.6 ready digital output . . . . . . . . . . . . . . . . . . . . 7 8.7 enable low current disable. . . . . . . . . . . . . . . 7 8.8 resistor pull-up value selection . . . . . . . . . . . . 7 8.9 hot swapping and capacitance buffering application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 application design-in information . . . . . . . . . 11 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 11.1 typical performance characteristics . . . . . . . . 14 11.2 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 15 12 test information . . . . . . . . . . . . . . . . . . . . . . . . 16 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 14 soldering of smd packages . . . . . . . . . . . . . . 19 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 19 14.2 wave and re?ow soldering . . . . . . . . . . . . . . . 19 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19 14.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 20 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 23 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 17.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 18 contact information. . . . . . . . . . . . . . . . . . . . . 23 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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